High-speed signal lines are commonly terminated by resistive loads selected to match the characteristic impedance of the signal lines and thereby cancel undesired reflections. Historically, the terminating elements have been implemented by discrete resistors connected to metal traces on a mother board or other printed circuit board. More recently, particularly in the domain of high-bandwidth memory systems, on-die termination structures have been provided, for example, on the integrated circuit die of a memory device or memory controller.
FIG. 1 illustrates a prior-art memory system 100 that employs an on-die termination scheme. The memory system 100 includes a memory controller 101 and pair of memory modules 103A and 103B, with each memory module coupled in parallel to a shared data path 102 (DATA), and each memory module (103A, 103B) coupled to a termination control line (TC1, TC2, respectively) to enable receipt of respective termination control signal from the memory controller. As shown in detail view 106, each of the memory devices 105 within a given memory module 103 includes a set of data input/output (I/O) circuits 1071-107N having a data signal transceiver 109 (i.e., output driver and signal receiver coupled to provide inbound data to and receive outbound data from I/O logic/memory core circuitry 115) and a switched termination structure 111 coupled in parallel to a respective data line 1171-117N of data path 112 (Data[N:1]), where data lines 1171-117N of data path 112 constitutes a subset of the data lines within data path 102. The switched termination structures 111 themselves each include a respective load element (R) coupled to the corresponding data line via a switch element (X), with each of the switch elements within the memory devices of a given memory module 103 coupled to a common termination control input, TC, to receive an incoming termination control signal. By this arrangement, the memory controller 101 may assert the termination control signal supplied to either of the memory modules 103 (i.e., via termination control lines TC1 and TC2) to switchably connect the load elements within the constituent memory devices of the memory module to respective lines of the data path 102. During write operations in which data is output onto the data path 102 to be received within a selected one of the memory modules (103A or 103B), the memory controller 101 asserts a termination control signal on the termination control line coupled to the non-selected memory module, thereby terminating the data path stub coupled to that memory module and suppressing undesired reflections. At the same time, the memory controller 101 deasserts the termination control signal supplied to the selected memory module thereby isolating the data path 102 from the on-die terminations within the memory devices 105 of that memory module to avoid undue signal attenuation. This operation of the memory controller is shown at 120 of FIG. 1.
Analysis shows that, unfortunately, the single-termination scheme of FIG. 1 may yield sub-optimal signaling performance due, at least in part, to impedance discontinuity that tends to result at the selected memory module when the on-die terminations within that module are decoupled from the data path 102. On the other hand, asserting the termination control signal at the selected memory module tends to unduly attenuate the incoming data signals, reducing signaling margin and increasing the likelihood of signaling errors.